1. Field of the Invention
The present invention relates to a thin-film transistor array device for an image display device formed by stacking, on a substrate, a thin film transistor having polycrystalline silicon or microcrystalline silicon as an active layer, to an electroluminescence (EL) display panel and an EL display which use the thin-film transistor array device.
2. Description of the Related Art
Thin-film transistors are used in drive substrates of display devices such as an organic electroluminescence (EL) display and a liquid crystal display and, at present, development towards high-performance is being actively pursued. In particular, amid demands for high current-driven performance in thin-film transistors following the increase in size and change to high-definition of displays, thin-film transistors that use a crystallized semiconductor thin-film (polycrystalline silicon or microcrystalline silicon) in an active layer have been gaining attention.
A low-temperature process using a processing temperature of 600° C. or lower is being developed as a crystallization process of semiconductor thin-films, in place of the already-established high-temperature process technology that uses a processing temperature of 1000° C. or higher. The low-temperature process does not require the use of expensive substrates such as heat-resistant quartz, and thus manufacturing cost can be reduced.
As part of the low-temperature process, laser annealing, which heats by using a laser beam, has been gaining attention. This pertains to irradiating a laser beam onto a non-single crystal semiconductor thin-film of amorphous silicon or polycrystalline silicon formed on a low-heat-resistance insulation substrate such as glass so as to melt the semiconductor thin-film by localized heating, and subsequently crystallizing the semiconductor thin-film in a cooling process thereof. A thin-film transistor is formed by stacking in which the crystallized semiconductor thin-film serves as an active layer (channel region). Since mobility of carriers increases, the crystallized semiconductor thin-film allows for increased performance of the thin-film transistor (For example, Japanese Unexamined Patent Application Publication No. 07-235490).
Meanwhile, a bottom-gate structure in which the gate electrode is disposed below the semiconductor layer is the predominant thin-film transistor structure. A structure of a bottom-gate thin-film transistor 1000 shall be described with reference to FIG. 32 to FIG. 36.
As shown in FIG. 32 to FIG. 36, the thin-film transistor 1000 is a multilayered structure including a substrate 1010, a first metal layer 1020, a gate insulating film 1030, a semiconductor film 1040, a second metal layer 1050, and a passivation film 1060.
A gate line 1021 and a gate electrode 1022 running from the gate line 1021 are formed in the first metal layer 1020 that is stacked on of the substrate 1010. Furthermore, the gate insulating film 1030 is formed above the substrate 1010 and the first metal layer 1020 so as to cover the gate line 1021 and the gate electrode 1022. In addition, the semiconductor film 1040 is stacked on the gate insulating film 1030 so as to overlap with the gate electrode 1022.
A source line 1051, a source electrode 1052 running from the source line 1051, and a drain electrode 1053 are formed in the second metal layer 1050 which is stacked above the gate insulating film 1030 and semiconductor film 1040. It should be noted that the source electrode 1052 and the drain electrode 1053 are disposed at opposing positions, and each overlaps with a part of the semiconductor film 1040. Furthermore, the passivation film 1060 is stacked on the gate insulating film 1030, the semiconductor film 1040, and the second metal layer 1050 so as to cover the source line 1051, the source electrode 1052, and the drain electrode 1053.
In the bottom-gate thin-film transistor 1000 as described above, the gate line 1021 and the gate electrode 1022 are formed in the first metal layer 1020 which is a lower layer than the semiconductor film 1040. In other words, the gate line 1021 and the gate electrode 1022 are already formed during the laser crystallization process of the semiconductor film 1040. More specifically, the gate line 1021 and the gate electrode 1022 need to have high heat resistance capable of resisting the temperature (approximately 600° C.) in the laser crystallization process.